1. Technical Field
The present invention relates to a power supply switching circuit that selects and outputs one power supply potential from among a plurality of power supply potentials. Furthermore, the invention relates to an electronic device or the like that uses such a power supply switching circuit.
2. Related Art
In electronic devices capable of receiving supply of power from a plurality of power supplies, a power supply switching circuit that selects and outputs one power supply potential from among a plurality of power supply potentials is used. In such a power supply switching circuit, there is a problem in that, when selecting one power supply potential from among the plurality of power supply potentials, a short-circuit current flows between input terminals of the plurality of power supply potentials.
As a related technology, in FIG. 1 of JP-A-2012-191705, a power supply switching circuit that selects one of an input power supply voltage V1 and an input power supply voltage V2 in accordance with the detection result of a detector 11 and outputs the selected input power supply voltage as an output power supply voltage V3 is disclosed. A control circuit 41 receives supply of a voltage V4 that is output by a diode OR circuit 42, and supplies the input power supply voltage V2 to a gate of a PMOS transistor 17, supplies the output power supply voltage V3 to a gate of a PMOS transistor 18, and supplies a ground voltage to a gate of a PMOS transistor 19. In that case, the PMOS transistors 17 and 18 turn off, the PMOS transistor 19 turns on, and the input power supply voltage V1 is output from an output terminal T3.
JP-A-2012-191705 (abstract; FIG. 1) is an example of related art.
In the power supply switching circuit of JP-A-2012-191705, cases are conceivable where it is desirable to select the input power supply voltage V2, even when the input power supply voltage V1 is higher than the input power supply voltage V2. However, as shown in FIG. 1 of JP-A-2012-191705, parasitic diodes exist in the PMOS transistors 17 to 19. Accordingly, when the input power supply voltage V2 is selected in the case where the input power supply voltage V1 is higher than the input power supply voltage V2, a short-circuit current will flow from an input terminal T1 of the input power supply voltage V1 to an input terminal T2 of the input power supply voltage V2 via the parasitic diode of the PMOS transistor 19 and the PMOS transistors 17 and 18.
As a result, there is a risk that breakdown of the PMOS transistors 17 to 19 will occur due to the short-circuit current. Also, in the case where a battery is connected to the input terminal T1 or T2, there is a risk that breakdown of the battery will occur due to over-current, or that, in the case where a power supply circuit is connected to the input terminal T1 or T2, the output voltage of the power supply circuit will rise or fall.